The switched mode power supply (SMPS) is a well-known type of power converter having a diverse range of applications by virtue of its small size and weight and high efficiency, for example in personal computers and portable electronic devices such as cell phones. An SMPS achieves these advantages by switching a switching element such as power MOSFET at a high frequency (usually tens to hundreds of kHz), with the frequency or duty cycle of the switching being adjusted using a feedback signal to convert an input voltage to a desired output voltage. An SMPS may take the form of a rectifier (AC/DC converter), a DC/DC converter, a frequency changer (AC/AC) or an inverter (DC/AC).
FIG. 1 shows a background example of an isolated SMPS, i.e. an SMPS which converts an input voltage Vin to an output voltage Vout whilst isolating the input from the output through a transformer. The SMPS 100 is provided in the form of a DC-to-DC converter which has on its primary side a half-bridge arrangement comprising two transistors, Q1 and Q2 (which may, for example, be field-effect transistors such as MOSFETs or IGBTs) and two capacitors, C1 and C2, which are connected between the power supply's inputs and to the primary winding 111 of the isolation transformer 110, as shown. The use of only two transistors to handle currents on the primary side makes the half-bridge configuration best suited to low-power applications requiring a low parts count. Although a half-bridge configuration is employed in the present example, other well-known topologies may alternatively be used on the primary side. For example, a full-bridge configuration with four transistors may be more suitable for higher-power applications. Alternatively, a push-pull arrangement can be used. In all these configurations, the switching of the transistors is controlled by a controller circuit (not shown).
FIG. 1 also shows a standard topology on the secondary side of the isolated SMPS 100, which includes a rectifying circuit and an LC filter connected to a load R. The inductor L of the LC filter is connected to the secondary winding 112 of the transformer 110. A centre-tap 113 referenced to ground is provided between a first portion 112a of the secondary winding 112 having n2 turns and a second portion 112b of the winding 112 also having n2 turns. In the present example, the rectifying network employs two diodes, D1 and D2, to yield full-wave rectification of the voltage induced in the secondary winding 112.
Power efficiency is, of course, a key consideration in the design of switched mode power supplies and its measure generally dictates the quality of the SMPS. Much research effort has therefore been directed at improving power efficiency. For example, Schottky diodes have extremely small reverse-recovery times and are therefore often used in order to minimize power losses associated with the diode switching. Alternatively, in order to improve the efficiency of the converter shown in FIG. 1 at higher current levels, the diodes D1 and D2 in the secondary side circuit in FIG. 1 can be replaced with a synchronous rectifier circuit comprising transistors, as shown at Q3 and Q4 in the SMPS circuit 200 of FIG. 2. Each of the switching devices Q3 and Q4 can take any suitable or desirable form, and are preferably field-effect transistors in the form of an N-MOSFET or a P-MOSFET, or an IGBT, for example. In the example of FIG. 2, the switch devices Q3 and Q4 have an internal body drain diode, which is not shown in the switch device symbol in FIG. 2. The switching of these transistors is controlled by a controller circuit (not shown), which may or may not be the control circuit controlling the switching of transistors Q1 and Q2.
The principles of operation of the SMPS shown in FIG. 2 will be familiar to those skilled in the art, such that a detailed explanation thereof is unnecessary here. Nevertheless, some of the basics will now be reviewed, to assist understanding of the present invention.
FIG. 3 shows the switching cycle diagram in accordance with which the gate electrodes of switches Q1-Q4 in FIG. 2 are driven by the SMPS controller circuit so that the primary side circuit generates a series of voltage pulses to be applied to the primary winding 111 of the transformer 110. In FIG. 3, “D” represents the duty cycle of the switching and “T” the switch period. The operation of the circuit during the four time periods 0 to DT, DT to T, T to (T+DT) and (T+DT) to 2T is as follows.
Time period 1 (0<t<DT): Switching device Q1 is switched ON while Q2 is OFF, allowing the input source at Vin to charge capacitors C1 and C2 via the primary winding 111 of the transformer 110. During this period, switching device Q3 is switched ON while device Q4 is switched OFF, allowing the source to transfer energy to the load R via the secondary winding 112 of the transformer 110. The output voltage Vout=n2/n1·Vin, where n1 is the number of turns in the primary winding.
The operation of the half-bridge isolated buck converter of FIG. 2 is to be contrasted with that of a flyback converter (or a combined forward/flyback converter), where energy is stored in an air gap provided in the transformer core during this period, to be subsequently released into the secondary side circuit when the primary winding of the transformer is not being driven. No such air gap is present in the core of transformer 110 shown in FIG. 2 or in any of the related circuits described in the following.
Time period 2 (DT<t<T): Switches Q3 and Q4 are both conducting and the current in the secondary side circuit therefore free-wheels through both portions of the secondary side winding in substantially equal measure, allowing the transformer flux to be balanced. In other words, the free-wheeling current generates two magnetic fluxes within the secondary winding with opposite directions in the vicinity of the centre-tap 113, yielding a net magnetic flux equal to zero in an area between the first and second portions of the secondary winding 112. Hence, the transformer core magnetization is balanced to zero, and the current in the primary winding during the free-wheeling period DT−T/2 is suppressed, thereby avoiding losses in the primary winding. Thus, the transformer volt-second balance is obtained over two switching periods so that a transformer reset is unnecessary.
Time period 3 (T<t<T+DT): In this interval, switching device Q1 is switched OFF while device Q2 is turned ON, allowing the capacitors C1 and C2 to discharge through the primary winding 111, exciting it with a voltage of opposite polarity to that in the first time period described above. On the secondary side, switch Q4 remains ON while switch Q3 is turned OFF, allowing the EMF generated in the lower portion of the secondary winding to drive a current through the inductor L.
Time period 4 (T+DT<t<2T): The operation proceeds as in time period 2 described above.
In order to have the transformer magnetic flux balanced (which is necessary to guard against the magnetizing current becoming large enough to saturate the transformer), the periods for which switches Q1 and Q2 are turned ON should be the same in each switch period. However, where the balance is imperfect, efforts have been focused on avoiding its adverse effects, such as by connecting a capacitor in series with the transformer's primary winding so that any excess voltage is dropped across the capacitor rather than the primary winding. In order to avoid a short circuit of the source or cross-conduction on the primary side, a delay is introduced between the turn-OFF of one switching device and the turn-ON of the other.
An alternative SMPS topology, with an untapped secondary winding, is shown in FIGS. 4A and 4B. The primary side of the SMPS 300A shown in FIG. 4A is the same as in FIGS. 1 and 2, although a full-bridge, for example, may alternatively be used. However, the secondary side comprises a diode full-bridge rectifying network with diodes D1-D4 connected to the load R via an LC filter. As with the example shown in FIG. 2, variants with semi- or full-synchronous rectification may be used in order to improve the power efficiency. An SMPS 300B with semi-synchronous rectification is shown in FIG. 4B. In both cases, the losses in the SMPS are mainly due to losses in the diodes.
The use of full- or semi-synchronous rectification on the secondary side as mentioned above is just one of the measures available to a designer seeking to improve the system efficiency. Efforts have also been directed to minimising switching and conduction losses in the transistors through the optimization of their structure, and to developing improved control architecture options (e.g. pulse skipping), as well as to reducing trace losses and other parasitics by appropriately integrating the switching devices into an IC package. Steps have also been taken to minimise losses in the passive components of the SMPS. Notably, resistive losses in the inductor windings, losses due to hysteresis and eddy currents in the transformer core, and losses in the capacitors due to their series resistance and leakage, and their dielectric losses, have all been addressed by efforts to improve the design of these components.
Yet despite these efforts, there still remains a need to further improve the power efficiency of the SMPS.